IC_DESIGN · ROL-0003
Semiconductor Layout & Verification Engineer
Take a clean schematic to a signed-off GDSII. You own DRC and LVS clean-up, layer handling, fill, and the scripting that makes verification reproducible rather than heroic.
OpenFull-TimeRemote-friendlyRemote
SPECIFICATION
- DEPARTMENT
- Physical Design
- DOMAIN
- Digital / Analog IC Design
- ARRANGEMENT
- Full-Time
- AVAILABILITY
- Immediate
- LOCATION
- Remote
- REMOTE
- Yes
- COMPENSATION
- PKR 250,000 – 380,000 / month
- POSTED
- 2026-02-09
- REFERENCE
- ROL-0003
RESPONSIBILITIES
- Produce custom layout for analog and photonic cells to foundry rules.
- Drive DRC, LVS, ERC and density checks to zero violations and document every waiver.
- Write the runset wrappers and regression scripts that make verification a one-command operation.
- Manage layer maps, fill and the final merge for tape-out.
- Maintain the GDSII release process, versioning and checksums.
REQUIRED_TOOLING
KLayoutCadenceSynopsysPython
WHAT WE NEED TO SEE
- Understanding of CMOS process layers, design rules and what each rule is protecting against.
- Experience in KLayout or a commercial layout editor.
- Scripting ability — Python or TCL — and a low tolerance for manual, unrepeatable work.
ADVANTAGEOUS
- Photonic layout experience: curvilinear geometry, non-Manhattan shapes, path-based routing.
- Exposure to a full tape-out cycle.
- Familiarity with PDK versioning and library characterisation.